Part two explains the workings of the JTAG (IEEE 1149.1) boundary-scan technology. In software development, perhaps the most critical, yet least predictable stage in the process is debugging. Many ...

JTAG (jay-tag) is one of the engineering acronyms that has been transformed into a noun, although arguably it is not so popular as RAM, or CPU. IEEE Std 1149.1-1990 IEEE Standard Test Access Port and ...

Enabling a robust on-chip debug capability is being recognized as animportant Design for Debug (DFD) capability for complex SoC and having DFDstandardization makes the Open Core Protocol (OCP) ...

This is the second in a series of three articles on silicon validation, introducing a new approach and some basic applications. Part 1 presented the silicon validation problem and the requirements of ...

In Part 1 in this series, we covered what an asymmetric multi-core application is, and what are the typical problems that can be encountered in such a system. Now that we have an understanding of ...

Hardware emulation continues to prove itself as a handy tool for hardware/software co-verification, where the objective is testing the integration of hardware and software. Part 1 of this series ...

Android Studio offers a rich palette of built-in development tools, and an even more abundant plugin ecosystem. The first three articles in this series focused on installation and setup and coding and ...